The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) devices incorporating memory arrays. More particularly, the present invention relates to an optimized read data amplifier and method for operating the same for use in the output data path of integrated circuit memory arrays.
Many types of dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (xe2x80x9cEDOxe2x80x9d), synchronous DRAM (xe2x80x9cSDRAMxe2x80x9d), double data rate (xe2x80x9cDDRxe2x80x9d) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a single pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Historically, integrated circuit differential amplifiers for use in reading out the contents of memory arrays have consumed a relatively large amount of power and a large amount of on-chip silicon area. For most conventional DRAM products with input/output (xe2x80x9cI/Oxe2x80x9d) widths of four, eight or sixteen bits, these deficiencies can be minimized. However, for advanced embedded DRAM products containing typical I/O widths of 128 bits or more (wherein each bit of the I/O width requires a read amplifier and more if pre-fetching is being employed) the deficiencies severely limit the performance and cell efficiency of the DRAM.
Disclosed herein is a fast, low power and small on-chip area consuming read data amplifier which is advantageously effectuated through the combined application of xe2x80x9ccurrent sensingxe2x80x9d and xe2x80x9cvoltage sensingxe2x80x9d techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned xe2x80x9coffxe2x80x9d when not in use and both data read lines (xe2x80x9cDRxe2x80x9d and xe2x80x9cDRBxe2x80x9d) are precharged xe2x80x9chighxe2x80x9d. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.
Particularly disclosed herein is an integrated circuit device including a read data amplifier coupled to first and second complementary read data lines and an intermediate data output. The read data amplifier comprises first upper and lower series connected transistors defining a first circuit node therebetween for coupling the first of the complementary read data lines to a tail node. Second upper and lower series connected transistors define a second circuit node therebetween to form the intermediate data output and couple the second of the complementary read data lines to the tail node. Control terminals of the first and second upper transistors are coupled to the first circuit node while a control terminal of the second lower transistor is coupled to the first data read line and a control terminal of the first lower transistor is coupled to the second data read line. A tail transistor couples the tail node to a first voltage source and first and second precharge transistors respectively couple the first and second circuit nodes to a second voltage source. First and second pull up transistors respectively couple the first and second complementary read data lines to the second voltage source and an enable input is coupled to a control terminal of the tail transistor and the first and second precharge transistors for enabling the read data amplifier.
Further disclosed herein is a read data amplifier coupling first and second data read lines to an output node for use in an integrated circuit device incorporating a memory array. The read data amplifier comprises a differential amplifier having first and second circuit nodes and first and second inputs thereof with the first input being coupled to the second data read line and the second input being coupled to the first data read line. An enable transistor is operative in response to a first state of an enable signal input for coupling the differential amplifier to a first voltage source and first and second precharge transistors are operative in response to a second opposite state of the enable signal for coupling the first and second circuit nodes respectively to a second voltage source.
Still further disclosed herein is a method for operating a read data amplifier coupled to first and second complementary data read lines in an integrated circuit device comprising a memory array. The method comprises precharging the first and second complementary data read lines and first and second circuit nodes of the read data amplifier to a first voltage level in response to a first state of an enable signal and terminating the precharge operation, applying data to the first and second complementary read data lines and substantially concurrently causing the first and second circuit nodes to assume a state corresponding to that of the first and second complementary read data lines in response to a second opposite state of the enable signal.